? semiconductor components industries, llc, 2002 august, 2002 rev. 1 1 publication order number: ntltd7900zr2/d ntltd7900zr2 power mosfet 9 amps, 20 volts, logic level nchannel micro8 leadless ezfets ? are an advanced series of power mosfets which contain monolithic backtoback zener diodes. these zener diodes provide protection against esd and unexpected transients. these miniature surface mount mosfets feature ultra low r ds(on) and true logic level performance. ezfet devices are designed for use in low voltage, high speed switching applications where power efficiency is important. typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. applications ? zener protected gates provide electrostatic discharge protection ? designed to withstand 4000 v human body model ? ultra low r ds(on) provides higher efficiency and extends battery life ? logic level gate drive can be driven by logic ics ? micro8 leadless surface mount package saves board space ? i dss specified at elevated temperature maximum ratings (t j = 25 c unless otherwise noted) rating symbol 10 secs steady state unit draintosource voltage v dss 20 v gatetosource voltage v gs 12 v continuous drain current (note 1) t a = 25 c t a = 85 c i d 9.0 6.4 6.0 4.3 a pulsed drain current (tp 10 s) i dm 30 a continuous sourcediode conduction (note 1) i s 2.9 1.4 a total power dissipation (note 1) t a = 25 c t a = 85 c p d 3.2 1.7 1.5 0.79 w operating junction and storage temperature range t j , t stg 55 to 150 c thermal resistance (note 1) junctiontoambient r ja 38 82 c/w 1. when surface mounted to 1 x1 fr4 board. 9 amperes 20 volts r ds(on) = 26 m (v gs = 4.5 v, i d = 6.5 a) r ds(on) = 31 m (v gs = 2.5 v, i d = 5.8 a) micro8 leadless case 846c http://onsemi.com device package shipping ordering information ntltd7900zr2 micro8 ll 2500 tape & reel source 1 gate 1 source 2 gate 2 drain drain drain drain (top view) pin assignment a = assembly location y = year ww = work week 1 marking diagram 7900 ayww 1 1 2 3 4 8 7 6 5 dd 2.4 k 2.4 k s 2 s 1 g 2 g 1 nchannel nchannel drain
ntltd7900zr2 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (note 2) (v gs = 0 vdc, i d = 250 adc) v (br)dss 20 24 vdc zero gate voltage drain current (v ds = 16 vdc, v gs = 0 vdc) (v ds = 16 vdc, v gs = 0 vdc, t j = 85 c) i dss 1.0 20 adc gatebody leakage current (v gs = 4.5 vdc, v ds = 0 vdc) (v gs = 12 vdc, v ds = 0 vdc) i gss 1.0 10 adc madc on characteristics (note 2) gate threshold voltage (note 2) (v ds = v gs , i d = 250 adc) v gs(th) 0.4 0.67 1.0 vdc static draintosource onresistance (note 2) (v gs = 4.5 vdc, i d = 6.5 adc) (v gs = 2.5 vdc, i d = 5.8 adc) r ds(on) 21 27 26 31 m dynamic characteristics input capacitance (v 16 vd v 0v c iss 7.4 15 pf output capacitance (v ds = 16 vdc, v gs = 0 v, f = 1.0 mhz ) c oss 237 400 transfer capacitance f = 1 . 0 mhz) c rss 4.1 10 switching characteristics (note 3) turnon delay time t d(on) 0.55 1.0 s rise time (v gs = 4.5 vdc, v dd = 10 vdc, i d =10adc r g =91 ) t r 1.17 2.0 turnoff delay time i d = 1.0 adc, r g = 9.1 ) (note 2) t d(off) 1.87 3.0 fall time (note 2) t f 4.8 7.0 gate charge (v gs = 4.5 vdc, i d = 6.5 adc, q t 12 18 nc (v gs = 4 . 5 vdc , i d = 6 . 5 adc , v ds = 10 vdc) (n t 2) q 1 0.7 s (note 2) q 2 3.7 sourcedrain diode characteristics forward onvoltage (i s = 1.0 adc, v gs = 0 vdc) i s = 1.0 adc, v gs = 0 vdc, t j = 85 c) (note 2) v sd 0.69 0.62 0.8 vdc 2. pulse test: pulse width 300 s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperatures.
ntltd7900zr2 http://onsemi.com 3 typical electrical characteristics v ds , draintosource voltage (v) 0.06 0.04 0.03 0.01 0 30 0 0 0.8 1.2 1.6 2.4 6 12 18 24 0 0 1 0.1 0.01 12 15 9 6 3 100 10 10,000 1000 2 0 12 15 18 9 6 3 0 i d , drain current (a) i d , drain current (a) i gss , gatecurrent ( a) i gss , gatecurrent (ma) v gs , gatetosource voltage (v) figure 1. gatecurrent versus gatesource voltage v gs , gatetosource voltage (v) figure 2. gatecurrent versus gatesource voltage figure 3. onregion characteristics v gs , gatetosource voltage (v) figure 4. transfer characteristics i d , drain current (a) figure 5. onresistance versus drain current 6 4 8 46810 6 12 18 24 30 r ds(on) , draintosource resistance ( ) 0 6 12 18 0 2 0.4 24 30 0.05 2.0 0.02 t j = 150 c t j = 25 c t c = 25 c t c = 125 c t c = 55 c v gs = 2.5 v v gs = 4.5 v v gs = 1.2 v 1.4 v 1.6 v 1.8 v 2.0 v 2.2 v 2.4 v 2.8 v 3.5 v 4.5 v 10 v
ntltd7900zr2 http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 8) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 20 0 0 1200 c, capacitance (pf) gatetosource or draintosource voltage (v) figure 6. capacitance variation 400 200 51015 600 800 1000 c oss t j = 25 c v gs = 0 v c iss and c rss are below 10 pf
ntltd7900zr2 http://onsemi.com 5 10,000 1000 100 2 0 81214 6 4 2 0 v gs , gatetosource voltage (v) q g , total gate charge (nc) figure 7. gatetosource r g , gate resistance ( ) figure 8. resistive switching time variation versus gate resistance 4 3 5 t, time (ns) 1 10 100 10 1 t j = 25 c i d = 6.5 a v ds = 10 v i d = 6.5 a v gs = 4.5 v t r t d(off) t d(on) t f v sd , sourcetodrain voltage (v) 0.1 0 i s , source current (a) figure 9. diode forward voltage versus current 0.4 0.6 0.8 1 1 10 0.2 t j = 25 c v gs = 0 v t j = 150 c t j = 25 c figure 10. onresistance variation with temperature 1.8 0.6 50 0 25 50 150 0.8 1.0 1.4 1.6 rds(on), draintosource resistance (normalized) t j , junction temperature ( c) 25 125 75 100 1.2 id = 9 a vgs = 4.5 v 0.2 0.4 50 0 25 50 150 0.3 0.2 0 0.1 v gs(th) , threshold variance (v) t j , junction temperature ( c) figure 11. threshold voltage 25 125 75 100 0.1 i d = 250 a 30 0 0 0.040 r ds(on) , draintosource resistance ( ) i d , drain current (a) figure 12. onresistance versus drain current and temperature 0.015 0.005 51015 0.020 0.035 20 25 0.010 0.025 0.030 t j = 125 c t j = 25 c t j = 55 c
ntltd7900zr2 http://onsemi.com 6 figure 13. thermal response r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 t, time (seconds) r(t), effective transient thermal resistance (normalized) 1 0.1 d = 0.5 104 102 101 1 0.2 0.01 0.02 0.05 0.1 10 1000 single pulse 103 100
ntltd7900zr2 http://onsemi.com 7 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 14. typical solder heating profile
ntltd7900zr2 http://onsemi.com 8 package dimensions micro8 leadless case 846c01 issue o a m n b 0.15 t 0.15 t 2 pl 2 pl pin 1 i.d. index area 8 7 6 5 1 2 3 4 top view p f e l 8 pl c1 c2 c4 c3 s u 4 pl r h detail z g 6 pl l 8 pl d w m 0.10 y t terminal tip note 5 l1 detail z j t k 0.10 t 0.08 t 8 pl 8 pl c aa aa seating plane side view view aaaa notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 4. dimension d applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. dimension l1 is the terminal pull back from package edge, up to 0.1 mm is acceptable. l1 is optional. 5. depopulation is possible in a symmetrical fashion. w y dim min max millimeters a 3.20 3.40 b 3.20 3.40 c 0.85 0.95 d 0.28 0.33 e 1.30 1.50 f 2.55 2.75 g 0.65 bsc h 0.95 1.15 j 0.25 bsc k 0.00 0.05 l 0.35 0.45 m 1.60 1.70 n 1.60 1.70 p 1.28 1.38 r 0.200 0.250 s 0.18 0.23 u 0.20 --- on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 291 kamimeguro, meguroku, tokyo, japan 1530051 phone : 81357733850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ntltd7900zr2/d ezfet is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
|
